OpenAI and Meta Standardize on Triton 3.5 for Heterogeneous AI Kernel Compilation
The next-generation Triton compiler brings unified intermediate representation across Nvidia Blackwell, AMD CDNA4, and custom cloud accelerators with zero code refactoring.
- Triton 3.5 introduces an extensible MLIR backend supporting cross-vendor execution without proprietary toolchains.
- Automated block scheduling and autotuning yield up to 92% of peak theoretical FLOPS on mixed FP8/FP4 gemm workloads.
- Meta and OpenAI formalize joint upstream maintenance to prevent vendor-locked compiler ecosystems.
SAN FRANCISCO — In an engineering pact aimed at curtailing vendor lock-in across accelerated computing stacks, engineers from OpenAI, Meta, and the broader PyTorch Foundation have formally released Triton 3.5, introducing a unified compiler architecture capable of targeting diverse hardware backends directly from high-level Python definitions.
The release directly challenges Nvidia’s historic CUDA moat by proving that kernel autotuning and intermediate representations (IR) can bridge performance disparities between competing silicon architectures without manual C++/CUDA rewrite cycles.
Figure 1: Machine learning intermediate representation (MLIR) optimization passes across heterogeneous accelerator targets.
Breaking the Monolithic Kernel Paradigm
For nearly a decade, extracting peak compute performance from emerging transformer architectures required hand-crafted CUDA kernels tuned by specialized performance engineers. With hardware architectures bifurcating across Nvidia Blackwell architectures, AMD’s CDNA 4 line, and hyperscale custom ASICs like Google TPU v6 and AWS Trainium, maintaining fractured kernel implementations became unsustainable.
Triton 3.5 solves this computational fragmentation by introducing Block-Level Multi-Level Intermediate Representation (MLIR) Dialects. Rather than targeting machine-specific assembly directly, developers author parallel matrix computations over tile abstractions in pure Python.
Python Tile Definition (@triton.jit)
│
▼
Triton MLIR Frontend
│
├── Memory Hierarchy Virtualization
├── Automatic Vectorization & Swizzling
└── Block Coalescing Engine
│
┌─────────┴─────────┐
▼ ▼
Nvidia PTX Backend AMD ROCm LLVM IR ASIC Custom VPU
(NVLink / HBM3e) (CDNA4 Fabric) (Systolic Array)Microbenchmarks: Nearing Hand-Tuned Parity
Initial third-party validation reveals performance parity that rivals—and in some memory-bound operations exceeds—proprietary vendor libraries such as cuBLAS and CUTLASS.
Under sustained evaluations conducting fused FP8 FlashAttention-3 operations on 128k token context windows:
- Nvidia B200: Triton 3.5 achieved 91.4% of theoretical peak Tensor Core throughput, compared to 92.1% recorded by native closed-source CUTLASS pipelines.
- AMD Instinct MI350X: Upstream code ran seamlessly with 89.8% peak FLOPS utilization without modifying a single line of host Python code.
- Compilation Latency: A modernized JIT caching layer dropped cold-start JIT invocation latency from 1.4 seconds down to 180 milliseconds per kernel variant.
“The AI ecosystem cannot scale if every model architecture revision demands three months of assembly re-optimization,” said Elena Rostova, lead compiler architect contributing to the Triton open-source consortium. “Triton 3.5 elevates the abstraction layer so models remain portable across whatever compute hardware wins on silicon economics.”
Availability and Ecosystem Deployment
The Triton 3.5 compiler toolchain is now integrated by default in nightly builds of PyTorch 2.6 and vLLM 0.9. Cloud orchestration engines including Hugging Face TGI and DeepSpeed have committed to migrating their primary default execution kernels to Triton by the end of Q4 2026.